SRAM - Memory Controller

Nexys2 Cellular™ RAM Controller

During the days of our final year project , we have been struggling as it consumed a considerable amount of memory which was not available as on-chip resources. We had to come up with a lookup table and the on-board PSDRAM of a Nexys2 board was used since the capacity of the on-chip Block RAM was not sufficient. Valuable Information on configuring the PSDRAM is presented in this post. By using this approach we completely eliminated the need for  calculations and lead to a computationally efficient design.The Digilent Nexys2  FPGA board contains a different memory device compared to the other available boards. It has a Micron MT45W8MW16BGX CellularRAM memory , which is a high-speed CMOS Pseudo SRAM device, developed for low power, portable applications. This particular device has a 128Mb DRAM (Dynamic Random Access Memory) core organized as 8Mb*16 bits and includes a few modes of operation; Asynchronous mode, page mode and burst mode. It would be convenient to make use of the Asynchronous mode of operation as the device goes into that mode on power-up. This mode uses the standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations are initiated by bringing CE#, OE#, LB# and UB# low while keeping WE# high. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations occur when CE#, WE#, LB#/UB# are driven low. During Asynchronous write operations, the OE# level is a “Don’t Care”, and WE# will override OE#, the CLK input must be held static LOW.

   Micron CellularRAM Functional Block Diagram

                                            

The Micron Cellular Ram device contains the standard SRAM control bus signals and the following 4 signals; ADV#, CRE, WAIT and CLK. Table 1 provides a detailed description of each Asynchronous mode signal used.


Table 1 SRAM signals

Signal	Type	Description
A [22:0]	Input	Addressed inputs during read\write operations
CLK	Input	Clock can be static low or high during asynchronous operations
ADV	Input	Address Valid: Can be held low during read\write operations
CRE	Input	Configuration Register Enable: When low, a read/write memory access
CE	Input	Chip Enable: Memory device activated when low
OE	Input	Output Enable: Enables output buffers when low
WE	Input	Write Enable: When low allows write operation
LB	Input	Lower Byte Enable DQ [7:0]
UB	Input	Upper Byte Enable DQ [15:7]
DQ	Input/Output	Data Input/Outputs
WAIT	Output	Asserted and ignored during read/write operations

Asynchronous RAM Read Timing Diagram

           

     Asynchronous RAM Write Timing Diagram

                                                           

I've Posted a link below where you can find an example application of the memory core we have written.Please note that I customized the core or rather the memory driver for a specific application which uses a lookup table approach. Definitely a certain modification is needed if you are planning to use this as the memory driver for your Design.

The Memory Driver - Download